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<title>RISC-V Core Debug Mechanism Comparison</title>
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</head>
<body class="article">
<div id="header">
<h1>RISC-V Core Debug Mechanism Comparison</h1>
<span id="author" class="author">Tim Newsome</span><br>
<span id="email" class="email"><a href="mailto:tim@sifive.com">tim@sifive.com</a></span><br>
<span id="revnumber">version 0.1,</span>
<span id="revdate">Dec 11, 2016</span>
<div id="toc" class="toc">
<div id="toctitle">Table of Contents</div>
<ul class="sectlevel1">
<li><a href="#_introduction">Introduction</a></li>
<li><a href="#_background">Background</a></li>
<li>
<ul class="sectlevel2">
<li><a href="#_definitions">Definitions</a></li>
<li><a href="#_goals">Goals</a></li>
<li><a href="#_metrics">Metrics</a></li>
</ul>
</li>
<li><a href="#_instruction_design">Instruction Design</a></li>
<li>
<ul class="sectlevel2">
<li><a href="#_overview">Overview</a></li>
<li><a href="#_rationale">Rationale</a></li>
</ul>
</li>
<li><a href="#_direct_design">Direct Design</a></li>
<li>
<ul class="sectlevel2">
<li><a href="#_rationale_2">Rationale</a></li>
<li><a href="#_considerations">Considerations</a></li>
</ul>
</li>
<li><a href="#_comparison">Comparison</a></li>
</ul>
</div>
</div>
<div id="content">
<div class="sect1">
<h2 id="_introduction">Introduction</h2>
<div class="sectionbody">
<div class="paragraph">
<p>The Debug Task Group is discussing two competing debug proposals. The main
difference between the specs is the core debug mechanic. One proposal revolves
around having the core execute instructions to implement all debugging. This is
known as Instruction design. (Historically, this has also been referred to
as SiFive/Tim Newsome/Full-Featured/one on the right.)</p>
</div>
<div class="paragraph">
<p>The other proposal defines a slightly more abstract interface where logically
GPRs and CSRs are accessed directly on a Debug Bus. This is known as the Direct
design. (Historically, this has also been referred to as ROA Logic/Richard
Herveille/Lightweight/one on the left.)</p>
</div>
<div class="paragraph">
<p>This document lives at <a href="https://sifive.github.io/debug-mechanism-comparison/">https://sifive.github.io/debug-mechanism-comparison/</a></p>
</div>
<div class="paragraph">
<p>If you&#8217;d like to contribute, the git repository is at
<a href="https://github.com/sifive/debug-mechanism-comparison">https://github.com/sifive/debug-mechanism-comparison</a></p>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_background">Background</h2>
<div class="sectionbody">
<div class="sect2">
<h3 id="_definitions">Definitions</h3>
<div class="dlist">
<dl>
<dt class="hdlist1">Run control</dt>
<dd>
<p>Halt, step, and resume a hart.  Set breakpoints.  Access GPRs, CSRs, other
registers, and memory.</p>
</dd>
<dt class="hdlist1">Self-hosted debug</dt>
<dd>
<p>Debugging where software running on the target system is the thing that
allows run control of the thing you&#8217;re debugging. Eg. running gdb on Linux,
and gdbserver on a bare metal target.</p>
</dd>
<dt class="hdlist1">External debug</dt>
<dd>
<p>Debugging a system without making any assumptions about the software
running on that system.</p>
</dd>
<dt class="hdlist1">Debug monitor</dt>
<dd>
<p>Software run on a bare metal system that allows for self-hosted debug.</p>
</dd>
<dt class="hdlist1">JTAG</dt>
<dd>
<p>De facto standard transport for external debug, but really developed for
post-manufacture test. It&#8217;s a simple 4-wire serial interface.</p>
</dd>
<dt class="hdlist1">Trace</dt>
<dd>
<p>Have a core emit what it’s doing in real time.</p>
</dd>
</dl>
</div>
</div>
<div class="sect2">
<h3 id="_goals">Goals</h3>
<div class="paragraph">
<p>A debug spec should allow a user to connect a debugger running on their
computer to a target system. The emphasis is on features that support debugging
systems that can&#8217;t or won&#8217;t support self-hosted debug.  The user should have
full access to the target’s resources, with the ability to download and execute
code, set breakpoints, access registers, and access memory.</p>
</div>
<div class="paragraph">
<p>The spec must describe how debug hardware behaves in such a way that software
written to debug one RISC-V system will also work to debug another. It must
also support multiple transports, and not be limited to JTAG.</p>
</div>
</div>
<div class="sect2">
<h3 id="_metrics">Metrics</h3>
<div class="paragraph">
<p>The following is a list of metrics that should be considered when evaluating a
debug solution. These are in rough order from most important to least
important, but not everybody will agree with any given ranking:</p>
</div>
<div class="dlist">
<dl>
<dt class="hdlist1">Ease of hardware implementation</dt>
<dd>
<p>How easy it to implement the spec in hardware?</p>
</dd>
<dt class="hdlist1">Ease of hardware verification</dt>
<dd>
<p>How easy it to verify the hardware. The smaller and more self-contained
each component is, the better.</p>
</dd>
<dt class="hdlist1">Hardware cost</dt>
<dd>
<p>How many gates does the implementation require?</p>
</dd>
<dt class="hdlist1">Scalability</dt>
<dd>
<p>How well does the design scale across all RISC-V core options, including
number of harts, configurations (RV32E&#8212;RV128), standard and custom extensions,
and compressed and extended instruction sets.</p>
</dd>
<dt class="hdlist1">Security</dt>
<dd>
<p>What are the security implications?</p>
</dd>
<dt class="hdlist1">Speed of debugging</dt>
<dd>
<p>How much (wall) time does it take to perform basic debug operations?</p>
</dd>
<dt class="hdlist1">Ease of software implementation</dt>
<dd>
<p>How easy is it to write a debugger that communicates with the hardware?</p>
</dd>
<dt class="hdlist1">Quick access</dt>
<dd>
<p>What is the impact on a running system if the debugger needs to access a
single word in memory, or a single CSR? This could be used to eg. sample a
counter or set a breakpoint on a system that cannot safely be halted for any
length of time.</p>
</dd>
<dt class="hdlist1">Usefulness for self-hosted debug</dt>
<dd>
<p>Are the hardware features added for external debug useful to help software
on the core debug itself?</p>
</dd>
<dt class="hdlist1">Usefulness for hardware bringup</dt>
<dd>
<p>How useful is the interface when bringing up hardware? This is not a
requirement per the goals, but certainly a nice-to-have.</p>
</dd>
<dt class="hdlist1">Ease of software verification</dt>
<dd>
<p>How easy is it to show that software will always do the right thing?</p>
</dd>
</dl>
</div>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_instruction_design">Instruction Design</h2>
<div class="sectionbody">
<div class="paragraph">
<p><a href="https://dev.sifive.com/documentation/risc-v-external-debug-support/">Latest Spec</a></p>
</div>
<div class="sect2">
<h3 id="_overview">Overview</h3>
<div class="paragraph">
<p>This design is focused on the debugger feeding a halted hart arbitrary
instructions, while keeping gate count to a minimum. This is necessary
functionality, and once it exists it can be used to accomplish all debug tasks.
To speed up certain repetitive operations, an optional Instruction Buffer can
be implemented. This is designed so that debug software can easily take
advantage of it if it exists, but doesn&#8217;t need separate code paths if it
doesn&#8217;t.</p>
</div>
<div class="imageblock">
<div class="content">
<img src="figures/overview.png" alt="Instruction Design Overview">
</div>
</div>
<div class="paragraph">
<p>When a hart halts (because it&#8217;s interrupted by the debugger or hits a
breakpoint), it starts fetching instructions from the DM. The DM communicates
this to the debugger, which feeds instructions. Data is exchanged by the hart
writing to special CSRs or using a memory-mapped interface. Below is an example
of what the debugger does to read memory.</p>
</div>
<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 1. Read from memory</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<thead>
<tr>
<th class="tableblock halign-left valign-top">Using CSRs</th>
<th class="tableblock halign-left valign-top">Using memory-mapped interface</th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><div><div class="olist arabic">
<ol class="arabic">
<li>
<p>Push <code>csrr s0, daccess32</code></p>
</li>
<li>
<p>Push address to read from</p>
</li>
<li>
<p>Push <code>lw s0, 0(s0)</code></p>
</li>
<li>
<p>Push <code>csrw s0, daccess32</code></p>
</li>
<li>
<p>Read data the hart wrote to the DM</p>
</li>
</ol>
</div></div></td>
<td class="tableblock halign-left valign-top"><div><div class="olist arabic">
<ol class="arabic">
<li>
<p>Push <code>lw s0, 0x400(zero)</code></p>
</li>
<li>
<p>Push address to read from</p>
</li>
<li>
<p>Push <code>lw s0, 0(s0)</code></p>
</li>
<li>
<p>Push <code>sw s0, 0x400(s0)</code></p>
</li>
<li>
<p>Read data the hart wrote to the DM</p>
</li>
</ol>
</div></div></td>
</tr>
</tbody>
</table>

<div class="paragraph">
<p>These operations can all be combined in a single transaction from debugger to
USB JTAG adapter, because of the way that errors are sticky when one occurs.
When all operations are done the debugger can check for errors, and retry with
longer delays if necessary.</p>
</div>
<div class="paragraph">
<p>The optional Instruction Buffer and Scratch RAM can be used to set up this
action without any interaction (steps 2 and 5 use Scratch RAM). This enables a
debugger to perform actions while halting the core just briefly.</p>
</div>
<div class="paragraph">
<p>The Instruction Buffer is also important in achieving fast download speeds.</p>
</div>
</div>
<div class="sect2">
<h3 id="_rationale">Rationale</h3>
<div class="paragraph">
<p>The debugger should be able to access anything that software can access.
Instead of adding extra data path logic to make that happen, the simplest way
is to allow the debugger to execute instructions on the core. That&#8217;s sufficient
for all debugging, including custom/future extensions.</p>
</div>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_direct_design">Direct Design</h2>
<div class="sectionbody">
<div class="sect2">
<h3 id="_rationale_2">Rationale</h3>
<div class="paragraph">
<p>One of the beauties of the RISC-V spec is that it’s implementation independent.
It defines the feature set and the requirements, but leaves the implementation
up to the user (implementer).  The debug specification should follow the same
route. It should describe the base and extensions registers and leave the
actual implementation up to the user.</p>
</div>
<div class="paragraph">
<p>There are many ways to implement this specification, e.g. using a debug
RAM/ROM, stalling the entire execution pipeline (for tiny implementations), or
stalling the current hart while keeping the execution units running in a multi-
threaded implementation.</p>
</div>
</div>
<div class="sect2">
<h3 id="_considerations">Considerations</h3>
<div class="paragraph">
<p>The main considerations while writing the Lightweight spec:</p>
</div>
<div class="olist arabic">
<ol class="arabic">
<li>
<p>The specification should be interface agnostic.</p>
</li>
<li>
<p>It should use a very simple interface</p>
</li>
<li>
<p>It should have minimal implications on the implementation of the actual CPU.</p>
</li>
<li>
<p>Reset, Halt, Single Step, Hardware Breakpoints, Address breakpoints,
Interrupt catching should all be supported.</p>
</li>
</ol>
</div>
</div>
</div>
</div>
<div class="sect1">
<h2 id="_comparison">Comparison</h2>
<div class="sectionbody">
<div class="paragraph">
<p>In each of the tables below, Memory-Mapped is on the left, and Instruction is
on the right.</p>
</div>
<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 2. Ease of hardware implementation</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Simple for simple designs, where the debugger reaches directly into the GPR
and CSR files. When designs get more complex (out-of-order execution, register
renaming), PC/GPRs may not exist in a single place.  Implementing this
interface in terms of instruction feeding is one option to deal with that.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">Simple for simple designs. The DM can reach directly into the core to push
instructions and exchange data. More complex for more complex designs. In that
case the simple implementation is to have the DM be memory-mapped, so the
processor can fetch instructions and perform accesses as usual even when
halted.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 3. Ease of hardware verification</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">In an implementation where the register files are accessed directly,
verification could be a significant burden.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">Requires relatively few changes to the CPU, which is the hardest part of the
design to verify.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 4. Hardware cost</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Per hart: 629 LUTs and 264 DFF. This is for a full featured debug unit, with 3
hardware breakpoints
</p><p class="tableblock">JTAG/Debug interface: 1180LUTs and 815DFFs. This is not really a fair
comparison as my jtag/debug interface handles burst mode accesses (it can read
an entire address range in one burst), handles multiple harts, and has a JSP
(emulated serial port).</p></td>
<td class="tableblock halign-left valign-top"><div><div class="dlist">
<dl>
<dt class="hdlist1">SiFive Coreplex, 0.11 spec</dt>
<dd>
<p>3,900 gates plus 600 gates per hart (RV32, no triggers)</p>
</dd>
<dt class="hdlist1">SiFive FE310 silicon, 0.11 spec</dt>
<dd>
<p>46,935 square &micro;m, or 1.17% of the total area of the SoC.</p>
</dd>
<dt class="hdlist1">IQ-Analog NanoRisc5, 0.11 spec</dt>
<dd>
<p>628 flops plus 1479 LUTs for one RV32, no triggers</p>
</dd>
</dl>
</div>
<div class="paragraph">
<p>Numbers include everything from JTAG TAP down to core changes.</p>
</div></div></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 5. Scalability</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">If core registers are added (eg. vector), debug address space needs to be
reserved, and hardware needs to be taught how to access the registers.
</p><p class="tableblock">The spec can be easily be extended to RV32/RV64/RV128.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">As long as any new state that&#8217;s added can be moved into GPRs, then the debug
hardware does not need to be modified.
</p><p class="tableblock">The spec already takes RV32/RV64/RV128 into account.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 6. Security</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">No clear security impact.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">No clear security impact. The spec does mention options for authenticating a
debug user. The fact that memory accesses go through the core is helpful if a
designer wants to allow eg. U-mode debugging but not M-mode debugging.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 7. Speed of debugging</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Should be equivalent.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">Download speed reported by gdb using 10MHz TCK, talking USB from inside a VM
to an Olimex USB-JTAG adapter:<br>
Start address 0x80000000, load size 16100<br>
Transfer rate: 121 KB/sec, 4025 bytes/write.<br></p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 8. Ease of software implementation</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Should be easy.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">Basic debugging is easy. Making the debugger perform well will require some
careful coding.
<span class="footnote">[<a id="_footnoteref_1" class="footnote" href="#_footnote_1" title="View footnote.">1</a>]</span></p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 9. Quick access</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Can be implemented in hardware, but will require a second port to register
files, or some way to stall the processor while a value is accessed.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">With optional Instruction Buffer and Scratch RAM in the Debug Module, a
debugger can set up arbitrary short instruction sequences to be execute as fast
as the processor can manage.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 10. Usefulness for self-hosted debug</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">A hart can access its own debug resources if it has access to the debug bus,
but there doesn&#8217;t seem to be a way to trap instead of stall. Once stalled the
hart cannot revive itself.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">Software breakpoints and hardware triggers can be used. Needs work for single
step.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 11. Usefulness for hardware bringup</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">In direct implementations, it&#8217;s likely still possible to access GPRs and CSRs
even when there are other issues with the core.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">If the core cannot execute instructions, it&#8217;s not possible to debug it in any
useful fashion.</p></td>
</tr>
</tbody>
</table>

<table class="tableblock frame-all grid-all" style="width:100%; ">
<caption class="title">Table 12. Ease of software verification</caption>
<colgroup>
<col style="width:50%;">
<col style="width:50%;"> 
</colgroup>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p class="tableblock">Should be a bit easier, since the software needs to be less smart.</p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock">More complex since the software contains more of the debug logic.</p></td>
</tr>
</tbody>
</table>

</div>
</div>
</div>
<div id="footnotes">
<hr>
<div class="footnote" id="_footnote_1">
<a href="#_footnoteref_1">1</a>. The simple implementation involves one round trip to the debug device
(USB-JTAG adapter) per scan, which tends to have a lot of overhead. Multiple
scans are required to perform almost any operation: at least 1 for an
instruction, and at least 1 for data. The only way to make the debugger
responsive is to combine multiple JTAG scans into a single request to the debug
device. This isn&#8217;t rocket science but it does require some thought.
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